Clock component: determine current (system) clock frequencies & dynamic frequency setting | Cypress Semiconductor
Clock component: determine current (system) clock frequencies & dynamic frequency setting
I'm struggling with the clock component. If I understand the clock component correctly, the API only allows for frequency change by modifying the divider values, so the source clock for the clock component must be known. Now, consider the case where someone uses dynamic control of the system clocks (e.g. HFCLK, IMO, SYSCLK, etc.) for power saving purpose.
Another case would be if someone has to change (only) the local clock for a component - the source clock frequency must be known. So, here the solution (or workaround) is not to use <auto> source clock, but fix it to e.g. HFCLK. This would at least ensure that the initial system frequency is known, thus enabling to calculate the correct divider values.
So, at least to be able to do such things, the frequencies must be kept track of. The question is: is this possible (or maybe already implemented, but overseen by me) ? Is there e.g. a preprocessor definition of (initial) HFCLK value, etc.?
In fact, the API must be extended in a way where the source clock frequency of a clock component can be determined, and the current (system) frequency values must be available at run-time - only having the dividers isn't enough.
What do you think?