Can't Configure a low frequency clock like say a 10 hz or even 100 hz | Cypress Semiconductor
Can't Configure a low frequency clock like say a 10 hz or even 100 hz
Hi,this problem is different from the RTC post, I'm just trying to do a simple debouncer circuit to test an issue.
PSOC 3.2 creater
PSOC 4M/4200M pioneerkit -44 version
System clock is HFCLK48Mhz
DEvice selected isCY8C4247AZI-M485 which is what the chip is on the M version of the pioneer kit.
When I do a regular clock of say 100 hz, I get this message:
Unable to create a divider of 480000 for clock "SwClock." The maximum possible divider for this device is 65536.
Too large of or too many clock dividers requested. There is a maximum number of clock dividers (used for digital, analog, and fixed function clocks) available depending on the device selected.
I can't change the souce from the HFCLock and I can't change anything in the design wide clock screen to have this clock get its source from the 32khz LFCLK.
I know from the datasheet that there are 16 dividers so I don't know why it won't let me create a low frq clock.
The examples projects don't work for this pioneer kit ONly earlier kits.
I even looked at
I tried adding another clock to divide the 48mhz down some, but when I add the second clock, it doesn't give me the first clock as a choice for a source. Only Auto and or HFCLock. Even under the existing tab it doesn't list the first clock
So how do I use a really low freq clock like I've seen used onother kits?