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Adding logic to SCB SPI SS and SCLK pins | Cypress Semiconductor

Adding logic to SCB SPI SS and SCLK pins

Summary: 0 Replies, Latest post by kmolden on 26 Feb 2014 05:00 AM PST
Verified Answers: 0
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kmolden's picture
26 posts

Hi guys,

I keep hitting a brickwall with my latest problem.

As I cannot upload all files to this post I have created a dropbox folder with the two projects and the corresponding output measured by a logic analyser.

I have to timeshare an SCB for SPI and UART. My initial problem is how to apply the logic required for my SPI (due to slave requiring two added clockcycles before and after each transaction) to an SCB block. 

I created a physical link between P0[6] and P0[5] and added the logic to pin P0[5].

As I control the SS pin manually, i used this pin as the second input to the the logic circuit. 

I don't see why i don't get the same response from the SCB design as i do in the working SPI design.

Please ignore the UART part at this stage.

Any help would be greatly appreciated.


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