Adc conversion hudge problem | Cypress Semiconductor
Adc conversion hudge problem
. ADC scanns 4 channels, one with single range detect, 2 with dif mode
.conversion triggered by software (ADC_startConv...) 4 sample averaging on all channels
.between conversions flash is written using API (EEPROM_WRITE..) into a single buffer ( interrupts not disabled)
.when entering intr read ADCSAR_SAR_INTR_REG, and written reg at the end
After few minutes of adc performace triggering interrups ( I can chatch this point) the interrupts stop firing anymore. reset is required and story repeats.
Conversion trigger bit is never cleared (acc. to TRM should be cleared by hardware). intr vector table is not modified during run.
I'm already contacting support case, but does not move thing forward.