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unstable ADC values

Summary: 5 Replies, Latest post by zabc on 11 Jan 2013 04:49 AM PST
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zabc's picture
User
17 posts

Hi,
i'm playing around with the ADC on the PSOC3, i've got the CY8CKIT-030. My Problem is even if i connect my input GPIO (P4.6) to VSSA, the rawvalue is very rough. It jumps around between bit 30 and bit 40, i expect a more stable value. Is it possible to get the noise smaller, so that it is stable on +-1 bit?
Sure a external voltage reference will help, i will try that, but isnt it possible to get more stability with the internal reference and without a filter?

I'm using:
-resolution: 16 Bit
-conversion mode: 2
-rate 2000sps
-input mode: single
-buffer gain: 1
-buffer mode: rail to rail
-Vref: internal bypassed on P0.3
-clock: internal

my code:

void main()
 {
Initial();

while(forever)
{
ADC_StartConvert();
ADC_IsEndConversion(ADC_WAIT_FOR_RESULT);
Rawdata = ADC_GetResult32();

sprintf(Buffer, "%ld", Rawdata);
UART_PutString (Buffer);
UART_PutCRLF(0x20);
}
}

so i get my rawdata displayed in my terminal.

Thanks

user_14586677's picture
User
7648 posts

Some additional thoughts.

 

If you look at power supply rail typical 200 mV+ of noise, with a 30 uV

LSB, thats ~ 6700 lsbs of noise in the system. PSRR of components can help,

but you can see a little bit of noise goes a long way to complicating sample

to sample readings.

 

Use differential measurements whenever possible, the CMRR of the diff amp, ADC

front end, will help with rejection and CM signal pollution. Clock the ADC at a multiple

of the decimator response frequency, specifically the zeroes, that helps with CM noise

suppression.

 

Look at the caps you use to suppress noise, polymers an order of magniitude better

Z(f) response. Ceramic disk as well, actually look at datasheets, not all caps are equal

in their ESR curves.

 

Regards, Dana.

user_1377889's picture
User
10803 posts

You didn't tell about using a bypass cap at port 0(3) did you connect one?

 

Bob

zabc's picture
User
17 posts

okay thanks - an external voltage reference and basically the difference mode helps to come close to my expectations. I had configured already an external bypass capacitor.

Now the values varies between -4bit and -7bit. Next i will try to add a lp-filter...

For now i'm happy - thanks a lot!

user_14586677's picture
User
7648 posts

If you have a hi res adc there is no end to the challenges to getting

low noise results, 16 bits with a 2V reference is 15 uV for 1/2 LSB.

 

Start by looking at your overall noise by using scope on infinite persistance,

and look at supply rails and inputs. That will give you the pk-pk noise you

are facing.

 

Here is an ap note on PSOC 3 ADC -

 

http://www.cypress.com/?docID=30483

 

More reference material that you want to know, attached.

 

Regards, Dana.

user_14586677's picture
User
7648 posts

If you have a hi res adc there is no end to the challenges to getting

low noise results, 16 bits with a 2V reference is 15 uV for 1/2 LSB.

 

Start by looking at your overall noise by using scope on infinite persistance,

and look at supply rails and inputs. That will give you the pk-pk noise you

are facing.

 

Here is an ap note on PSOC 3 ADC -

 

http://www.cypress.com/?docID=30483

 

More reference material that you want to know, attached.

 

Regards, Dana.

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