UART 1.20 --> 1.50 on PSoC3 | Cypress Semiconductor
UART 1.20 --> 1.50 on PSoC3
I have been using the 1.20 UART on an RS-485 bus configuration and the network ceases to operate when undating to 1.50 (I changed the number of bits setting after the update, but nothing else).
When I put a logic analyzer on the bus it looks like the 1.20 version introduced a slight amount of inter-byte delay, as indicated by little pulses on the Tx Enable line, but this is not so with the 1.50 version. I am only sending about 12 bytes in a typical packet, but this seems to be long enough for differences in the baud rate clocks to create a CRC error.
When I stop using buffered transmission and thus introduce a small inter-byte delay, the network operates as before.
What I would really like to be able to do (and have for the last 10 years) is set the number of stop bits for Tx to 2 and set Rx to 1. This would be a simple way to still use buffered transmission and get a little delay for re-framing each byte. There may be a way to select an inter-byte delay through the API, but I haven't found it.
I'm curious if others have faced the same situation, and what some possible solutions are. Plus if enough chime in, may Cypress will address this...