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Trouble resetting I2C Master after glitches. | Cypress Semiconductor

Trouble resetting I2C Master after glitches.

Summary: 4 Replies, Latest post by dchung on 07 Dec 2011 01:27 PM PST
Verified Answers: 0
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dchung's picture
27 posts

 Hi, I am trying to reset an I2C Master after inserting random glitches to the hardware I2C.  I have not been successful on resetting the hardware.  It seems that once I2C Master is hanged due to random glitches, it stop responding even though the hardware is reinitialized.  I am testing this with no slaved attached, so all transaction are NAKed.














Even after those routines are called, the I2C_MCSR_BUS_BUSY  bit in I2C_MCSR_REG remains '1'.  Can anyone help with resetting the I2C hardware?


uday's picture
Cypress Employee
569 posts
  • Are you using Fixed function I2C Master component or UDB based component. In case of the UDB based component there is an hardware Reset terminal which resets the hardware state of the entire hardware module you could try the same. You could connect a pin to this reset terminal and make it zero. Or you could connect a Control Register Component(Present in Digital --> Registers Folder in component catalog) to this terminal and configure it for one bit operation and make this register toggle between a logic an logic zero to reset the I2C component. 
  • How are you inserting Glitches and could you give some information about these glitches.


MXMat's picture
1 post

Dear all,

Unfortuneatley I am experiencing a similar problem:

My setup is as follows (silicon PsoC3, production):

I2CMaster_0 (fixed function, 400kHz) connected to one slave of specific type
I2CMaster_1 (UDB, 400kHz) connected to one slave of same type
I2CMaster_2 (UDB, 400kHz) connected to one slave of same type
I2CMaster_3 (UDB, 400kHz) connected to one slave of same type

From time to time the master implemented as FF stalls and the communication breaks down.
I'm unable to reset the FF I2CMaster.
Due to resource limitations I cannot implement all 4 masters as UDBs

Any thoughts?

Matthias Arnold

dasg's picture
Cypress Employee
730 posts

Hi Matthias,


Is the communication from the FIxed Function I2C Master breaking down everytime or only when glitches is introduced?


Is the hardware configuration of the I2C master set right? Both the pins SDA and SCL should be Bidirectional with Drive Mode as Open-Drain Drives Low. The external pull-up resistors used should be used and the length of the cable must be within the maximum permissible limits. Are all these requirements taken care of? This is to confirm that there is no timing violation.




dchung's picture
27 posts

adding   I2C_CFG_REG = 0u   works.

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