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SPIM reading external memory incorrectly | Cypress Semiconductor

SPIM reading external memory incorrectly

Summary: 43 Replies, Latest post by hli on 02 Jan 2017 06:27 AM PST
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brian's picture
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Basically, the SPIM will rotate bits as they are read into the PSoC3.... WARNING - not all chips present this problem! Some PSoC chips are NOT PRONE to this rotation! Other chips CONSISTANTLY show the problem!

Yes, a demo project is available on request! brian@genesysinst.com

Project: Create an SPIM with the normal IO (not bidirectional), mode 0. Disconnect the CS (SS) and connect to non-hardware pin. Chip used is a CY8C3866PVI-021ES2. I tried the DVK and it too gives this problem!

I'm using Ramtron FM25V05 as external memory, so grab a data sheet and notice that the word is similar (not identical!!!) to the Apps Note EP60810 - I.E. a multiple data word must be sent while the CS is low. I have pins 3 and 7 tied high, by the way. Well, the write needs two dips in the CS, but...

Speed - 3MHz, internal clock. Leave the buffers set at 4. I use the RESET pin to hold the SPIM non-functional and tri-state the IO as the Ramtron needs to be read by another processor. No interrupts.

Read/write various bit patterns as a BLOCK (one start address, many data). I need to block move data on occasion for my project.

I get bit rotations! Writing 16 (0x10) locations of "0x80" results in a READ of "0xC0" for the 0x10 locations! All the same!

Heres a list of some stuff I tried: 0x00 -> 0x00, 0xff -> 0xff, 0x55 -> 0x2a, 0xaa -> 0xd5, 0x80 -> 0xc0, 0x01 -> 0x00; 0x88 -> 0xc4, 0x11 -> 0x08.... Curiously, reading in, say, 0x15 locations does not reveal that the 0x11'th location contains incorrect data. You might expect this if the bit pattern is rotating to the next byte in the stream. So the stream is not polluted? Or can I say that?

Thoughts?

Stub for 2575603's picture
User
99 posts

Just to make sure I'm completely clear, you are using the SPI communication interface to talk to an external memory, correct?

 

Also, what version of PSoC Creator are you using?

 

-Bobby

dp
dp's picture
User
1 post

 I also see a similar problem.

In my case I have the following conditions CPU clock 48MHz. SPI clock 400KHz and SPI Master in Mode 00. Reads return data with a 1 bit shift so 5 is actually returned as 2. I can see on the scope that the data is correct. If I slow the CPU clock to 24MHz but keep the SPI clock at 400KHz everythings is fine.

I'm use Psoc3 ES3 silicon with Beta5 creator

My read function is as follows :

unsigned char IF_ReadRxData(void)

{

   while ((SPI_GetTxBufferSize()!=0));   // Wait for Tx FIFO empty ( incase any transfers are left)

   while(!(SPI_ReadTxStatus() & 0x10 )); // SPI idle,  becuase FIFO can be empty but not idle

   SPI_ClearRxBuffer();  // Clear old data 

   SPI_WriteTxData(0xFF);  // Send Data to trigger the transfer  

   while(SPI_GetRxBufferSize() ==0 );  // Wait for data to come in.

   return SPI_ReadRxData();  // Return Data

}

 

Also waiting for SPI idle is very slow. What is the best way to do the above. If you can't be sure the previous transfer has finshed before trying to read the next byte.

Thanks

 

 

dasg's picture
Cypress Employee
730 posts

Hi dp,

 

Instead of using "while(SPI_GetRxBufferSize() ==0 ); " to ensure that the dummy byte has been transmitted, can you try using "while(!(SPIM_1_ReadTxStatus() & SPIM_1_STS_SPI_DONE));" ?

Let us know if you can observe any improvement.

 

Regards,

dasg

 

dasg's picture
Cypress Employee
730 posts

brian,

From the description you have provided, it is clear that the received value is right-shifted by 1 bit.

You need to open the configuration tab of MISO input and unsynchronize it by unchecking the "Input Synchronized" from the "Input" tab. This should be able to solve the issue.

Let us know if this works.

 

Regards,

dasg

 

 

Binbe's picture
User
5 posts

Hi,

I have a problem using too the FRAM FM25V05. I send a quantity of 0b0001000 in the memory ( or 0x10) and when we want to read it we have several errors. In my case, instead of receiving 0x01 we receive 0x00 ...

I use 16MHz CPU with 4MHz SPI clock.

Here a screenshot of my scope showing my problem: (1 = SPI clock, 2 = a trigger that shows where we have a 'read error')

 

The trigger (channel 2) on this attached picture should fall on a falling edge of the clock, in this case it falls before one half period (average) of the falling edge of the SPI clock.

Have someone any idea about our problem ? What can be the origin of this reading error ?

Regards,

Albin.

 

PS: The writing process succesfull, we have only problem on reading ..

Binbe's picture
User
5 posts

Just something that i have to add, channel 2 is the data that we get from the FRAM. We should get the rising edge of the data from the falling edge of the clock till the next falling edge of the clock, here the "1" falls before the next falling edge ... that is our problem.

if someone have an idea, let me know :)

user_1377889's picture
User
10803 posts

Deducting from your last description: the data-pulse from the fram is not long enough. Are there any parameters for your memory that can be set differently?

And Are you using the right Mode for the SPI Master?

Bob

hli
user_78878863's picture
User
2759 posts

According to the data sheet, you are using SPI mode 0 (CPOL=0, CPHA=0). This means the data should be set at the falling flank of the clock (which it does) and be read with the rising flank. This is where it fails. The frequency is OK, the FRAM can go up to 40MHz. But did you try with a lower frequency? Do other read operations fail too (e.g. the device ID)?

What looks suspicious to me is the high swing on the data line. Could it be that you don't have a proper blocking capacitor for the FRAM? Or maybe the signal lines are too long

Binbe's picture
User
5 posts

@Bob Marlowe: Hi Bob, thanks for your reply. We are using Mode 0 SPI Clock and about the memory's parameters all is ok.

@hli: You are right about our problem, that data falls before the falling edge of our clock. At higher frequencies we have same/similar errors (@8MHz SPI Clock, @16MHz ...).

What do you mean by writing "Could it be that you don't have a proper blocking capacitor for the FRAM" ?

About signal wires they are shorter as possible.

Thanks for your help.

hli
user_78878863's picture
User
2759 posts

You should have a 100nF capacitor between Vcc and GND on your chip. Make it as close to the cip as possible. It avoids drops in the power supply when the power consumtion of the chip changes (which happens everytime it starts to work).

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