SPIM master component trouble with SCLK | Cypress Semiconductor
SPIM master component trouble with SCLK
PSOC Creator version is 3.3 SP2
SPIM component version 2.5
I am trying to use a SPIM master component on a CY8C3446-AXI099 running @5V.
PSOCMOSI is mapped to port 0.1, SCLK is mapped to Port 0.3. Both pins are set to Resistive pull up as the target device operates @3.3V. Slave can tolerate 5V inputs.
SPIM component is set to internal clock @1000kbps.(tried even lesser upto 100kbps)
On scoping, it appears that the SCLK is not toggling enough to clock out the MOSI data. MOSI shows fast transitions, SCLK shows ramps of very low frequency.
Connecting MOSI output to SCLK pin on schematic confirms that the output driver is fine and MOSI signal is being repeated on both pins 0.1 and 0.3 correctly.
Interchanging MOSI and SCLK pins so that what was MOSI is now SCLK and vice-versa, the problem of the sleepy SCLK pin shifts to the MOSI pin..
This indicates to me that there is some error in either my implementation or the SPIM component. SCLK does not seem to come out of the pin.
Can someone please help me understand what I am doing wrong? If this has been redressed before, a link to the answer will be helpful.