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Sample/Track & Hold problem | Cypress Semiconductor

Sample/Track & Hold problem

Summary: 1 Reply, Latest post by Bob Marlowe on 20 Oct 2013 12:05 PM PDT
Verified Answers: 0
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user_224686894's picture
3 posts

Did peak detector on the component subject. We must remember the amplitude of the square pulse duration > 10us.

The component has configured as follows.

- "Sample & Hold"

- "Internal"

- "Falling edge"

Synchronized pulse from the Pulse Converter component, 2us, who was started by digital sygnal under investigation immediately.

On output of Sample & Hold I was see clear 0!

P.S. In main.c component was started, not forgot to do this...

user_1377889's picture
9301 posts

Welcome in this forum!

You may attach a "Workspace Bundle" (Creator "File"-menu), so we all can check settings, program etc.

Best is to use ms internet explorer, chome doesn't work for attachments.



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