Sample and Hold Droop Rate estimation | Cypress Semiconductor
Sample and Hold Droop Rate estimation
To estimate the minimum sampling frequency that could be used for S/H (Sample and Hold) module in PSoC 3/5,
we need to know the droop rate of the S/H circuit. Droop rate of the S/H circuit
refers to the rate at which the voltage across the hold capacitor(inside the S/H)
drops with respect to time in hold mode.However, the droop rate of the S/H module is not characterized.
I have attached two projects “sample_hold_test” and “sample_SH” that can be used for estimating the maximum hold time and minimum sample speed for 10% voltage droop respectively.
The same projects could be reused by minor modifications in the firmware for different voltage tolerances.
All the tests were done on CY8CKIT-030 PSoC3 DVK.
I hope this would help for those looking for S/H droop rate.