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Sample and Hold Droop Rate estimation | Cypress Semiconductor

Sample and Hold Droop Rate estimation

Summary: 1 Reply, Latest post by danaaknight on 25 Sep 2013 09:16 AM PDT
Verified Answers: 0
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lsen's picture
Cypress Employee
22 posts


To estimate the minimum sampling frequency that could be used for S/H (Sample and Hold) module in PSoC 3/5,
we need to know the droop rate of the S/H circuit. Droop rate of the S/H circuit
refers to the rate at which the voltage across the hold capacitor(inside the S/H)
drops with respect to time in hold mode.However, the droop rate of the S/H module is not characterized.

I have attached two projects “sample_hold_test” and “sample_SH” that can be used for estimating the maximum hold time and minimum sample speed for 10% voltage droop respectively.
The same projects could be reused by minor modifications in the firmware for different voltage tolerances.

All the tests were done on CY8CKIT-030 PSoC3 DVK.

I hope this would help for those looking for S/H droop rate.


user_14586677's picture
7646 posts

Just a couple of suggestions -


1) Show people how to compute, for a given resolution, the necessary max droop rate.

For example, if max A/D in = 2.5V, resolution 16 bits, then droop should be < 2.5 / 2**17

for 1/2 lsb max droop error.


2) Also in comments suggest the importance of temp, what the source of leakage is,

and how it behaves.


Regards, Dana.

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