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PSOC3 UDB counter capture issues | Cypress Semiconductor

PSOC3 UDB counter capture issues

Summary: 1 Reply, Latest post by Bob Marlowe on 03 Nov 2015 11:39 AM PST
Verified Answers: 1
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Mariano Bochatay's picture
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I am trying to use a DMA channel triggered by the interrupt on capture feature of a 24-bit UDB counter but the counter seems to be triggering it just once. If I am not getting it wrong XaxCtr_STATICCOUNT_LSB_PTR is a pointer to the last captured value while XaxCtr_STATICCOUNT_LSB is the capture value pointed to by the former (from the code generated for the counter by psoc creator).

#define XaxCtr_STATICCOUNT_LSB (*(reg32 *) \

      XaxCtr_CounterUDB_sC24_counterdp_u0__F0_REG )

#define XaxCtr_STATICCOUNT_LSB_PTR ( (reg32 *) \

      XaxCtr_CounterUDB_sC24_counterdp_u0__F0_REG )

In the example project I use the same counter configuration that I am using in my application. I am capturing the counter by banging a control register bit while the counter is being fed by a 1 Hz clock. At the start of the program the counter (up & down) is preset to half its counting range so we can go up or down without reaching overflowing or underflowing it. This preset is captured but it stops working there even when the counter keeps counting up which is veryfied by reading it into a variable in the line

ctrval = CY_GET_REG24(XaxCtr_COUNTER_LSB_PTR);

I added a second transaction to the DMA channel that reads the counter status byte in order to clear the interrupt as stated in page 22 of the component data sheet. Is the reading of the status register by a DMA transaction a valid way to clear the interrupt flag? What would be the right way to do it if not?

I am attaching a sample project with the problem (or the doubts about me missing some point). Another worry regarding the counter is the atomicity of the readings (either capture or counter register). While researching for this problem I stumbled upon a thread dealing with that problem ( and I experienced myself a few strange readings but they were more in the form of a zero reading than an byte overlap because the counter was not changing.

Thank you and best regards

user_1377889's picture
9301 posts

Is there any reason why you do not use the APIs for reading/setting your counter but accessing some cryptic registers?

Reason for not working as expected will be the interrupt signal from counter not returning to zero level as you already assumed.

I would connect an isr-component to the nrq output of the DMA and read the status of the counter to clear the interrupt.



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