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PSoC3 DELSIG ADC cofigured as single ended and input range Vssa to Vdda and 8bit res | Cypress Semiconductor

PSoC3 DELSIG ADC cofigured as single ended and input range Vssa to Vdda and 8bit res

Summary: 5 Replies, Latest post by hli on 13 Apr 2013 06:45 AM PDT
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user_101879199's picture
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PSoC3 DELSIG ADC cofigured as single ended and input range Vssa to Vdda and 8bit res gives near Full Scale reading when input is 2.5v (Cy8CKIT-001 is set to 5v and all VddIO jumpers are set to Vdd. The Vref is set at Vdda/4 so... 2.5v and is not changable.... BUT for an input range of Vssa to Vdda shouldn't Vref be Vdda/2 instead of Vdda/4? Why am I unable to change Vref? Why should it be Vref/4 instead of Vref/2? What am I missing? Thanks

Tim Miner (AKA TDGM)

Will now try some Level Shift experiments.

user_14586677's picture
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user_14586677's picture
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7648 posts

Not sure why the problem, from the DS -

 

 

Regards, Dana.

hli
user_78878863's picture
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The data sheet states explicitely that the reference setting is choosen automatically when you select "Vssa to Vdda" as input range (see page 14). (When setting Vdda to 3.3V Vref is set tot Vdda/3)

But could it be that you have set a buffer gain != 1 ?

 

user_101879199's picture
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Hi All and Thank You ...

The buffer gain is still set to 1. I did find the note on Data Sheet page 14 and my math says if Vref is 3.3, I get a Full Scale range of 1.1v.

When I read the table 3 entry for Vssa to Vdda... I see that it says input range not full scale range. Is it stated or assumed that these are different? I came into this assuming that input range was the same as full scale range. However, I can see many possible reasons this implementation (PSoC) would define them differently. Perhaps because I did not use any other input configurations, I was not exposed to those definitions or reasons.

So, has anyone seen (in PSoc docs) something that says something like: ...?

The buffer and, when used, the level shifter will operate over the identified input range.

or

The ADC's Full Scale Range (or span) is the Vref or multiple of Vref identified and that all voltages applied to the ADC's inputs must fall within the input range ... blah blah... Note that Full Scale Range is not the same as Input Range.

Perhaps the team that coded the Wizard for the DelSigAdc covered the issue without clarifying the issue (enough for me at least).

The ADC example software for single ended operation worked exactly like my code. I missed the fact that it says:

If the effective input value is 0 volts then digital output displayed on the LCD is 0x0000. If the effective input voltage is 1.024V, then output displayed on the LCD is 0xFFFF.

I should have seen that and said: "Full Scale Range is not the same as Input Range."

BUT WAIT... that did not fix it either. I finally stripped things out of top design that I was not using yet. I had to keep comparing the working code (Cypress example for single ended input) and it came down to this:

I had a line in the main for loop that did not say if (ADC_IsEndConversion(ADC_WAIT_FOR_RESULT))... instead, it said ADC_IsEndConversion(ADC_WAIT_FOR_RESULT)); no "if", a following semicolon, and no open/close braces with the variable = ADC_GetResult16(); code within.

Now, the ADC goes up to FF at 4.95volts instead of 2.49volts.... NOTE that even when I fixed the first mux measurement, I still had the problem on both measurements until I got that second copy (for the second measurement) out of the for loop.

Exposure != Experience

Tim Miner

 

 

 

hli
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When you look at the data sheet, pages 10+11, you see how the input range and the value range are matched. There is nothing limiting the value range to Vref. When you select "Vssa to Vdda" as input range, Vref gets selected as Vdda/4. But this still gets you the full value range, so input=Vssa->0x00, input=Vdda->0xffff. You value range is the 0 up to 4*Vref.

So your solution was to really wait thill the conversion had been finished? Reading the result to soon will always lead to wrong results...

Everything is working now?

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