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PSoC Creator SIO Problem | Cypress Semiconductor

PSoC Creator SIO Problem

Summary: 5 Replies, Latest post by U2 on 20 Feb 2011 05:22 AM PST
Verified Answers: 0
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user_1443307's picture
13 posts

I have Vddios configured at at 5V, 3.3V, and 2.8V.  I want to use the SIO output pins to drive 5V levels.  I have the output pins configured for strong drive, slew rate slow, drive level: vref.  I've tried both 8mA and 25mA drive current with the same results.  I get the following error when I try to build:

Location for SIO port "Spare_0" is invalid; SIO ports must align with the start of an SIO pair.


The user assigned location for the SIO port specified is incorrect. An SIO port must align with the start of the physical SIO pair.

The fitter will now quit.

The SIO pins are designated correctly for the CY8C3866AXI-40 package that I am using.

I get the same results with both the Beta Creator and the latest Production version.  If I delete the pin generating the error, the error just moves to the next SIO.

Any ideas?

kiku's picture
Cypress Employee
64 posts

Hello wholloway,

You need to use only Port 12 for SIO pins. Also set the drive mode to Open Drain and connect your SIO to 5V with a resistor so that you can drive the external device.




user_1443307's picture
13 posts

Thanks for the response.

I'm still not sure what was causing the error message.  It went away when I changed the levels to CMOS instead of VREF.  I had overlooked the fact that SIO can't source a voltage higher than its vddio.  I am now configured as you recommend.  I'm not convinced I won't see the error again the next time I attempt to specify VREF instead of CMOS - I think a bug is lurking in there somewhere.

dasg's picture
Cypress Employee
730 posts

Hi wholloway,


SIO cannot source  voltage more than the voltage set in its Vddio setting. However you can connect it to higher voltage system (upto 6V) by using external pull up resistors and configuring the SIO to open drain.

The error you have encountered may be due to different configuration setting for the SIO pins in a given pair.

In PSoC3/5 the Voltage supplied to I/O pins (Vddio) are divided into 4 quadrants. Hence there are 4 Vddio available- Vddio0, Vddio1, Vddio2 and Vddio3. There is a pair of SIO (Port 12 pins) present in every quadrant.

Vddio0 - P12[2]:P12[3]

Vddio1 - P12[6]:P12[7]

Vddio2 - P12[4]:P12[5]

Vddio3 - P12[0]:P12[1]

Hence two pins a a given pair cannot have different voltage configuration.

The appropriate voltages for Vddio can be set at the following location in the project:

.cydwr > System > Voltage Configuration


Let us know if this works.




user_1443307's picture
13 posts

Like I said, my problem was solved by changing the input thresholds to CMOS or LVTTL and changing the output to VDDIO with the drive set to Open Drain, Drives Low.

However, if I change both pins on a SIO port  setting the input threshold to 0.5 Vref and the output drive level to Vref (leaving the drive set to Open Drain, Drives Low, in the General tab),  the fitter spits out:

Error: apr.M0014: Location for SIO port "I2C_Clk_SIOREF_0" is invalid; SIO ports must align with the start of an SIO pair. (App=cydsfit)

uday's picture
Cypress Employee
569 posts

 Hello Wholloway,

In PSoC3 there are 2 types of IOs namely GPIO and SIO. There only 8 pins available as SIO. These are available on PORT12. The SIO pins are tolerant to input voltages higher than the I/O supply voltage and can sink up to 25 mA current. The input threshold levels 0.5 VDDIO, 0.4 VDDIO, 0.5 VREF, VREF is available only with an SIO. Selecting  0.5 x VREF and VREF threshold options add reference Terminal to the Digital Input Pin component. This allows to route external reference from other components such as DAC or a Pin. 

If you need the 24mA current capability or the above mentioned input thresholds, the pins have to mapped to PORT12 in the project.CYDWR file.

Hope this helps.


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