PSoC Creator SIO Problem | Cypress Semiconductor
PSoC Creator SIO Problem
I have Vddios configured at at 5V, 3.3V, and 2.8V. I want to use the SIO output pins to drive 5V levels. I have the output pins configured for strong drive, slew rate slow, drive level: vref. I've tried both 8mA and 25mA drive current with the same results. I get the following error when I try to build:
Location for SIO port "Spare_0" is invalid; SIO ports must align with the start of an SIO pair.
The user assigned location for the SIO port specified is incorrect. An SIO port must align with the start of the physical SIO pair.
The fitter will now quit.
The SIO pins are designated correctly for the CY8C3866AXI-40 package that I am using.
I get the same results with both the Beta Creator and the latest Production version. If I delete the pin generating the error, the error just moves to the next SIO.