You are here

PSOC 3/5 COMPONENT DESIGN CONTEST 1 | Cypress Semiconductor

PSOC 3/5 COMPONENT DESIGN CONTEST 1

Summary: 7 Replies, Latest post by hli on 12 Dec 2012 04:42 PM PST
Verified Answers: 0
Last post
Log in to post new comments.
rahulram's picture
Cypress Employee
115 posts

Attaching the Specifications. I will make sure that from the next week, the contest specification is put as a sticky note.

Sorry for the delay.

Last Date for submission : 12/17/2012 12:00 PM (PDT)

 

Regards,

Ramnath R K

hli
user_78878863's picture
User
2759 posts

I have one question though: the up/down input should not be a physical connection, but a component configuration, right? (having it as an input on the symbol and then saying it should be a 'configuration lable' confuses me somewhat).

Thanks,

hli

rahulram's picture
Cypress Employee
115 posts

Yes, it need not be a separate input. It shall only be a component parameter.

 

Regards,

Ramnath R K

hli
user_78878863's picture
User
2759 posts

I have another question though (even multiple ones :), regarding #4 of the specification:

  1. assuming load goes high at t1, and clock goes high at t2, should load_values(t1) or load_values(t2) be loaded?
  2. when load stays high for multiple clock periods, are the values loaded one time or each time?
  3. when load goes high multiple times in a single clock period, should the first or the last values be loaded?

And last but not least: where shall be send the components to? Just post them here?

rahulram's picture
Cypress Employee
115 posts

 hli,

1. When load remains high for multiple clock cycles, at every rising edge of the clock, output the value that is available  at load_value input. Do not worry if the value is changing or not. Input to the system is something that we cannot control and hence if the load is high, then at every clock edge, just output the value that is present in the input load_value.

2. Load getting hit several times on a single clock pulse is something like a load signal racing over the system. I can assure you that load signal frequency is much less than the clock signal. 

3. The simple protocol would be,  if load is high, then at every rising edge of the clock, output the value available at the rising edge's instant on the load_value .

 

mail the component to

rkrm@cypress.com - Moderator PSoC 3

ancy@cypress.com - Moderator PSoC 5

hli
user_78878863's picture
User
2759 posts

Thanks for the clarification. This makes the implementation much easier (the way I understood it originally resulted in a counter having 3 different input clocks, and I was not able to synthesize this with Creator, despite having it work in a simulation).

rahulram's picture
Cypress Employee
115 posts

 Thats great. Waiting to evaluate your component. We are just going to start this with simple questions, but on the go; the specifications will get much harder. 

There will also be an increase in the reward points for those questions.

Expecting a great response from the customers.

 

hli
user_78878863's picture
User
2759 posts

Done :) But since it's a PSoC5 component, you won't get to see it... (But one could make an additional one for PSoC3, it shouldn't make a difference after all...)

Log in to post new comments.