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PSoC 3-5 Component Design Contest | Cypress Semiconductor

PSoC 3-5 Component Design Contest

Summary: 14 Replies, Latest post by hli on 30 Apr 2013 03:00 AM PDT
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rahulram's picture
Cypress Employee
115 posts

 Sorry people, there was a small issue with the previous two posts and i couldn't include the projects individually.

I am attaching a word document carrying the verilog code of all the 4 deisgns, appropriately numbered.

 

Please do go through the appropriate code and vote for the best design.

 

Regards,

Rahul Ram

 

 

user_1377889's picture
User
10803 posts

Well, despite the fact that I'd like to vote for my code (of course) (BIG SMILEY) there is something that I think I did NOT misunderstand and as such is reflected in my code:

The exercise-text said: Load should occur following the clock after the rising EDGE of the Load-signal. This implies (at least for me) that the load signal is asynchronous @ posedge and the Load-signal may(!!) return to zero before the clock's rising edge which will perform the load.

I found out, that a project using that component "burnt" a lot of macrocells, could that be done better for instance with a datapath solution?

 

Bob

hli
user_78878863's picture
User
2759 posts

I specifically asked this question in the forum, and it got clarified (load should be evaluated on each rising clock edge).

user_1377889's picture
User
10803 posts

I know, I've red your posts, but I'm too obstinate to accept a weakening of the specs when the original exercise could be solved (broad grin!)

 

Bob

hli
user_78878863's picture
User
2759 posts

And actually I think that you code also might not work in the case you mention: whe load and clock go high in the same instant you get a race condition(and when I tried a similar solution, Creator warned me also about that, or even refused to compile the design).

hli
user_78878863's picture
User
2759 posts

And if you really follow the original spec: load should happens only once, even if the load signal stays high for multiple clock periods. In your code, loading the values, and re-setting the load_flag happens at the same time, which might or might not work... (all these thing were the reasons for me to ask - really following the spec would need an interesting state machine, with 3 different input signals, all asynchronous to each other)

user_1377889's picture
User
10803 posts

Yes, that was my solution, Load, Clock and !Reset are all async in my design and it DID compile.

 

Bob

hli
user_78878863's picture
User
2759 posts

Since this was several months ago:

  • will there be future contests?
  • has a winner been selected for this one?

Thanks!

user_1377889's picture
User
10803 posts

No winner, no points, no thanks, no criticim, no further attempt, a couple of "NOs". I was a bit dissapointed 'cause I thought that the idea was pretty good, but as we all could see the carrying through could have been a lot better.

 

Bob

hli
user_78878863's picture
User
2759 posts

Yes, this is only one of many instances of marketing campaigns which have silently stopped :(

user_39759791's picture
User
357 posts

 Probably there was not the response expected. I didn't take part ecause it was close to the holidays. Although I doubt I would have had any chance against you guys xD

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