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multple I2S components

Summary: 4 Replies, Latest post by Wavelength on 30 Jul 2012 01:18 PM PDT
Verified Answers: 0
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gennadyp's picture
2 posts


Sorry for repost, but it seems that there are 2 different forums at Cypress with different categories ..
I need to design 4 channel usb audio streamer (Psoc3 -> PC over usb).
I've been told by tech support that it's possible, and I will need 2 I2S components to get audio data.

It's all fine. The problem is that I2S components operate ONLY in master mode.
According to the datasheet, when I issue an API call I2S_Start(), the I2S component starts generation of the SCK (bit clock) and WS (LR clock).
But since I start two I2S components sequentially, issuing 2 API calls,
these components are not going to be synchronous.
And since I can use only one component (both are in a master mode !) to synchronize external DSP (source of audio),
the input audio data on the second I2S component is NOT going to be synchronous to it's CLK and WS clocks.

I tried to contact tech support with this question, they told me that in order to reach a person who knows about it,
I need to create a web case, which will be answered in 24 hours.
It's already 24 x 3 hours, and no response :-(

Does anyone have an idea how to deal with this problem ?
Or multiple I2S just don't work in this situation ?

Thank you,

rahulram's picture
Cypress Employee
115 posts


sorry for that. we will get back to you quickly with the answer.

roit's picture
Cypress Employee
221 posts

 Hi Gennady,

Sorry for the delay in response. It may look that calling the I2S_Start() for the two different  I2S's would make the out clocks (WS and SCLK) not synchronous to each other but it is not true. I2S component and its clocks are dictated by the main clock at the input of the two I2S components. For synchronous audio, you have to source both the I2S with the same clock. As this I2S input clock is same for both the I2S in synchronous audio, the  output WS and SCLK from I2S will be synchronous. Also, you can use the WS and SCLK from any one of the I2S to sync the DSP with which you want to communicate audio data.

If you are concerened about the difference between the two I2S by one sample (which may happen if there is some amount of time between starting the two I2S components), then you can start the I2S input clock after enabling the RX side. Be careful that calling I2S_Start() does not start the transmission or reception of audio data. You need to call I2S_EnableRx() to start reception of data (which is your case) or I2S_EnableTx() for transmission of audio data. After calling this, you can start the I2S input clock so as to make sure that there is no audio sample lag between the two I2S.

Apart from above, there are few other additions that you need to do so that this synchronous USB audio streaming is possible. One of the critical one is generating the I2S input clocks and Master clock using the USB SOF (start of frame). Currently, PSoC Creator does not have a component to do this clock generation. It is in the roadmap but I am afraid I may not be able to provide you a timeframe. Hope this helps.


Rohit Kumar

gennadyp's picture
2 posts

Hi Rohit,

as far as I understand, the last paragraph of your post means, that my goal - multiple channel audio 2.0 streaming - can not be reached on a PSOC at this time.

Is this right ?

Thank you,


Wavelength's picture
8 posts

You could specify the enumeration as Asynchronous instead of Adaptive. See Class 1 USB Audio. I would suggest looking at the Class 1 as the Class 2 is much broader and cannot be supported by PSOC because it requires HS USB.

This would require the specific I2S Master Clocks to be external to the PSOC processor and some additions made to link these external clock(s) to the I2S framework. The good news is with this sort of design your overall jitter will be reduced by a really high amount which means your DAC output will be significantly better.

You would also need to change the enumeration tables and add a USB IN channel and work through the specification so that your dac chips don't under run or over run.



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