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MFI USBTOI2S question | Cypress Semiconductor

MFI USBTOI2S question

Summary: 3 Replies, Latest post by U2 on 25 Mar 2011 12:26 PM PDT
Verified Answers: 0
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user_96997098's picture
User
3 posts

ERROR :Routing of asynchrononus signal Clock_1 as a clock to UDB component "\AudioClkGen:UDB_ACG:div:Div:u0\" is not supported unless a UDB Clock/Enable component is used

user_96997098's picture
User
3 posts

When I build USBtoI2S code,display error:Routing of asynchrononus signal Clock_1 as a clock to UDB component "\AudioClkGen:UDB_ACG:div:Div:u0\" is not supported unless a UDB Clock/Enable component is use

Base on above question,How to solve it?

 

 

user_96997098's picture
User
3 posts

the above sample code is Digital Audio - RDK - 2.2.0_20101117

U2
uday's picture
Cypress Employee
569 posts

Hello David,

The clock that goes in to any of the UDB based component in PSoC3 could be of synchronous or asynchronous nature(synchronous to the BUS Clock). It is necessary to have the clock input to the I2S component synchronous. To achieve this,

  • you need to place a "UDB Clock Enable" component on your Topdesign
  • Connect the input clock to the input of the UDB Clock enable component
  • Set to "true"

This should fix the issue. If you are still not able to resolve the issue please raise a case so that we can track and fix it.

-Udayan

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