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Machester Decoder using Psoc | Cypress Semiconductor

Machester Decoder using Psoc

Summary: 17 Replies, Latest post by pvkv on 18 Nov 2015 11:20 PM PST
Verified Answers: 8
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Chetan's picture
User
16 posts

Hi everyone, I am Chetanya and i am  new to Psoc and  presently for the completion of my final year graduation project wants manchester deoder to be implement on psoc3, its very urgent and it will be of great help if i would be provided assistance from very basic level.

Thanks

dasg's picture
Cypress Employee
730 posts

Hi Chetanya,

 

A Manchester Encoder can be created using PSoC in a fascinating yet simple way using an SPI Master Component and an XOR Gate.

By XORing the MOSI and the SCLK of the SPI Master, the Manchester Encoded data can be obtained.

 

When the MOSI data is high, the clock polarity will invert (high to low transition), when MOSI data is low, the clock is passed as it is, resulting in a low to high transition.

 

 

The clock output is not given to the decoder unit. The decoder should have a clock recovery system and decode the Manchester encoded data.

 

 

dasg's picture
Cypress Employee
730 posts

A Manchester decoder can be created in PSoC 3/5 in a complete hardware implementation !

 

What you need is just an XOR Gate, a Delay Unit (in the form of a Counter or PWM) and a D Flip-Flop.

The clock recovery unit is to be implemented.

 

Refer to the waveform shown below:

 

 

The Serial data is the Manchester encoded data. Now, assuming that the first bit is 0, upon transition, the PWM is used to generate a delay of 3/4 of the time period of the encoded data. For example, if data rate of encoded data is 100 micro sec, then the terminal count of the PWM should occur at 75 micro sec.

Then the data is sampled, and is held in the D Flip Flop till the next 3/4 bit period.

This signal is called as Polarity_invert. These two signals are XORed to get the serial clock.

 

The figure below shows the implementation.

 

dasg's picture
Cypress Employee
730 posts

The decoder when implemented in PSoC Creator will appear as shown below:

 

 

Here, assume that the Manchester encoder data rate is 10 Kb/s, then the time period is 100 micro seconds.

The PWM is configured such that the terminal count occurs at 75 micro seconds.

 

A project is created which has both Manchester encoder and Decoder. The encoder sends a data 0x34.

This data is decoded and the clock is recovered.

The oscilloscope snap shot is shown below:

 

 

Yellow waveform is the Manchester Encoded data.

Blue waveform is the Decoded data (0x34).

Pink waveform is the recovered clock.

 

The data is observed on the rising edge of the recovered clock.

From the above waveform, it can be seen that the output obtained is 00110100 (0x34).

 

Hence, it can be seen that the decoder can be implemented in hardware. Only the PWM needs to be started in main code.

dasg's picture
Cypress Employee
730 posts

 

Yellow waveform = Manchester encoded data

Blue waveform = Decoded data (0x34)

Pink waveform = Recovered clock.

 

The data is sampled on the rising edge of the recovered clock. From the waveform above, it can be seen that the output obtained is 00110100 (0x34).

Hence, Manchester decoder can be implemented in PSoC 3 in hardware without any intervention from the CPU. Only the PM Component is to be started in main.c at the beginning. The D Flip Flop and XOR gate are implemented in the UDB.

Chetan's picture
User
16 posts

 Thank you very much for the help regarding manchester encoder, however in the DECODER part i m still having trouble.

ACTUAL DATA RATE FED INTO SPI MASTER :  32KHZ 

i am giving data serially through SPI master to convert it into manchester encoding, after that the data is being received after XORING in a timer which is providing 3/4th bit delay (config. of timer, 8bit resolution, period 6, continuous run mode, trigger on rising edge, no capture, external clock of 256 KHZ)

 And the output of D-flipflop is connected to the serially in of the SHIFT REGISTER with its external clock attached to the out of the XOR i.e our clock output. configuration of SHIFT REGISTER is only shift in and as soon as data gets into it, it is being read.

On LCD the output coming is not what was expected.

Please guide me

This is the code in the main.c 

 

#include <device.h>

uint8 temp;

void main()

{

    /* Place your initialization/startup code here (e.g. MyInst_Start()) */

SPIM_1_Start();

Timer_1_Start();

Clock_1_Start();

ShiftReg_Start();

LCD_Char_1_Start();

    /* CYGlobalIntEnable; */ /* Uncomment this line to enable global interrupts. */

    SPIM_1_WriteByte(0x91);

CyDelay(100);/* Place your application code here. */

temp=ShiftReg_ReadRegValue();

LCD_Char_1_PrintInt8(temp);

for(;;)

    {

      

    }

}

 

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desh's picture
Cypress Employee
9 posts

 Hi Chetanya,

      For this decoder to work ,the  first bit(MSB) of the received data at the decoder  should be 0.If the MSB is 1 (which is the case here),the decoded data will be erroneous. 

desh's picture
Cypress Employee
9 posts

 I have a working project here.

desh's picture
Cypress Employee
9 posts

To receive a byte which has its MSB '1', configure the SPIM to transmit 9 bits. For example if the SPIM is configured for  9 bit transmission, the decoder can correctly decode 0x91 and the same is displayed on the LCD.The configuration is shown below.

dasg's picture
Cypress Employee
730 posts

Hi Chetanya,

 

In addition to the suggestions made by  spectrum, these are the following changes made to the project in order to accomodate transfer of multiple bytes:

 

1) Set the "Data Bits" to 9 in the SPI_Master. Retain the ShiftReg Length to 8 bits. This will enable the use of numbers from 0 to 255 (0x00 to 0xFF). Remember that the MSB (9th bit) must be 0.

2) To transfer multiple bytes, a counter is used in the form of Look Up Table (LUT) which will count from 0 to 8. When 9th shift is done, the output from NOR gate is High which is used to generate a rising edge trigger to the ISR.

3) This ISR is used to store the value of shift register into a temp variable.

4) After all the bytes are received, the values are displayed on LCD.

 

In this project, two arrays are sent. "hello" and 0x5A, 0xA5, 0x34 and 0x98.

 

The project is attached along with this comment.

dasg's picture
Cypress Employee
730 posts

The final schematic is as shown below:

 

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