Attached is the project for interfacing SPI EEPROM with PSoC3. AT93C46E SPI EEPROM module was interfaced with PSoC3 in this project.
Attaching the project
Try to use ms internet explorer, chrome seems to have problems here
If you have trouble in uploading the project, you can mail the archived project to me at email@example.com
I'll upload the project in the forum for you.
I'm uploading the project on behalf of PSoCRulez.
Some thoughts -
1) Should not
while( !( SPIM_ReadTxStatus() & SPIM_STS_SPI_DONE ) );
be typed as
while( !(SPIM_ReadTxStatus() == SPIM_STS_SPI_DONE ) );
2) What is the purpose fo the cap on sclk ? You state "reliability" but
generally speaking terminating a clock line with C is undesired.
One other thing, you have all the interrupts enabled, but I do not
see any associated ISR's to service them ? Or placement of a
ISR component on an ISR output ?
Your signal SS pin, is that a CS for EEPROM ? If so you are meeting the
stated conditions -
WRITE (WRITE): The Write (WRITE) instruction contains the 16 bits of data to be written into
the specified memory location. The self-timed programming cycle, tWP, starts after the last bit of
data is received at serial data input pin DI. The DO pin outputs the ready/busy status of the part
if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO indi-
cates that programming is still in progress. A logic “1” indicates that the memory location at the
specified address has been written with the data pattern contained in the instruction and the part
is ready for further instructions. A ready/busy status cannot be obtained if the CS is brought
high after the end of the self-timed programming cycle, t .