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Interfacing SPI EEPROM with PSoC3 | Cypress Semiconductor

Interfacing SPI EEPROM with PSoC3

Summary: 11 Replies, Latest post by danaaknight on 21 Jan 2013 07:02 AM PST
Verified Answers: 0
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HIMA's picture
Cypress Employee
389 posts

Attached is the project for interfacing SPI EEPROM with PSoC3. AT93C46E SPI EEPROM module was interfaced with PSoC3 in this project.

HIMA's picture
Cypress Employee
389 posts
HIMA's picture
Cypress Employee
389 posts
HIMA's picture
Cypress Employee
389 posts
HIMA's picture
Cypress Employee
389 posts

 Attaching the project

user_1377889's picture
User
10803 posts

Try to use ms internet explorer, chrome seems to have problems here

 

Bob

dasg's picture
Cypress Employee
730 posts

Hi PSoCRulez,

 

If you have trouble in uploading the project, you can mail the archived project to me at dasg@cypress.com

I'll upload the project in the forum for you.

dasg's picture
Cypress Employee
730 posts

Hi All,

 

I'm uploading the project on behalf of PSoCRulez.

user_14586677's picture
User
7648 posts

Some thoughts -

1) Should not

 

while( !( SPIM_ReadTxStatus() & SPIM_STS_SPI_DONE ) );

 

be typed as

 

while( !(SPIM_ReadTxStatus() == SPIM_STS_SPI_DONE ) );

 

2) What is the purpose fo the cap on sclk ? You state "reliability" but
generally speaking terminating a clock line with C is undesired.

user_14586677's picture
User
7648 posts

One other thing, you have all the interrupts enabled, but I do not

see any associated ISR's to service them ? Or placement of a

ISR component on an ISR output ?

 

Regards, Dana.

user_14586677's picture
User
7648 posts

Your signal SS pin, is that a CS for EEPROM ? If so you are meeting the

stated conditions -

 

WRITE (WRITE): The Write (WRITE) instruction contains the 16 bits of data to be written into
the specified memory location. The self-timed programming cycle, tWP, starts after the last bit of
data is received at serial data input pin DI. The DO pin outputs the ready/busy status of the part
if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO indi-
cates that programming is still in progress. A logic “1” indicates that the memory location at the
specified address has been written with the data pattern contained in the instruction and the part
is ready for further instructions. A ready/busy status cannot be obtained if the CS is brought
high after the end of the self-timed programming cycle, t .

 

Regards, Dana.

 

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