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How to perform JTAG Testing on unprogrammed PSOC3 CY8C3444AXI-116 | Cypress Semiconductor

How to perform JTAG Testing on unprogrammed PSOC3 CY8C3444AXI-116

Summary: 1 Reply, Latest post by SmartPSoC on 13 Nov 2013 12:32 AM PST
Verified Answers: 0
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jwanderl's picture
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I have a design with a unprogrammed PSOC3 CY8C3444AXI-116.  I'm trying to develop a BSCAN test so I can test the device.  We have the device in a JTAG chain all by itself.  The infrastructure test works fine.  Once I try to run the interconnect test (or any other tests), all the nets fail.  the detailed JTAG diagnostics information shows that all the nets are stuck at zero.

I couldn't find any info in the data sheet.  but the BSDL file for this devcie contains this note at the end of the sheet:

"This CY8C3XXXX_XXX TQFP100 BSDL file supports 1149.1 testing only after "&
  "two of the following conditions are satisfied: "&
  "1. The JTAG port is enabled. "&
  "2. All IOs are pre-configured to drive out fast strong high/low. "&
  "JTAG access can be enabled either through programming NV-Latch "&
  "bits appropriately or through using test-port acquisition protocol. "&
  "The IOs may be pre-configuration either by writing port "&
  "configuration registers directly through a test port, or relying "&
  "on a programmed boot sequence which does that to complete automatically. "&
  "Testing other IO configurations requires changes to this file and "&
  "the pre-configured IO configuration.";

See it makes sense that this would be my problem.  I believe condition #1 is satisfied since I am using a Corelis controller which would use the TMS signal for enabling the JTAG port (since the infrastructure test passes, it would be safe to assume JTAG is enabled).  But condition #2 requires a pre-configuration...this obviously hasn't been done.  We didn't want to spend a lot of resource time creating a program so we can JTAG BSCAN test the device.  Would any one be able to lend some info on how to satisfy this conditions quickly?  Would there be a program available already?

greatly appreciate any help you can offer.

Jeff W

SmartPSoC's picture
Cypress Employee
68 posts

 The default drive mode of the pins is ihigh impedance analog mode. In this drive mode the output buffer is disabled and hence boundary scan test cannot be done in this mode since the external hardware cannot control the output state of 

the IO.  The IO_PRT_PRT(X)_PRT register have to be written with 0x0C to set the port X in strong drive mode. This can be done by 

 programming the device with an empty project and setting all the pins to this setting as part of maincode. 


The above API has to be repeated for all the ports.



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