How to cram my design into the PSoC ? | Cypress Semiconductor
How to cram my design into the PSoC ?
We had a problem with a PCB manufacturer. They populated our boards with CY8C3666LTI-201 instead of CY8C3666LTI-027. Now my design won't fit into the chip! I need 5 more 'blocks', (I assume UDBs?).
I'm currently trying to optimise the design, and I'm now only 4 blocks short. However, the error messages aren't that helpful. The UDB is a complex object, and it's not clear exactly what parts of the UDB it isn't able to place. Is it the Datapaths, PLDs, what? As far as I can tell, the .rpt file only reports on the last successful build, and so doesn't give any clue as to why a build failed.
Is there any way I can analyse my problem? What features should I try to optimise? What features might I need to get rid of to fit my design?
Thanks for any advice.