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Design 4 Code | Cypress Semiconductor

Design 4 Code

Summary: 0 Replies, Latest post by rahulram on 23 Dec 2012 09:52 AM PST
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rahulram's picture
Cypress Employee
115 posts

 `include "cypress.v"

`ifdef counter4bit_ALREADY_INCLUDED

`else

`define counter4bit_ALREADY_INCLUDED

//`#end` -- edit above this line, do not edit this line

 

//`#start body` -- edit after this line, do not edit this line

 

module counter4bit (

    Count_Out,

    Min,

    Max,

    Load_Val,

Clock,

Load,

Roll_Enable,

Reset

);

output [3:0] Count_Out;

output  Min;

output  Max;

input   Clock;

input   Load;

input   Roll_Enable;

    input   [3:0] Load_Val;

input   Reset;

parameter Up_Down = 1;

 

    reg     [3:0] Count_Out; // current count value

    reg     Min; // min output

    reg     Max; // max output

 

    // assign output lines to registers

 

    // whatever happens to the counter, set min and max accordingly

    always @(Count_Out)

    begin

        Min=(Count_Out==0);

        Max=(Count_Out==15);

    end

    

    always @ (posedge Clock or negedge Reset)

    begin

        // handle async reset

        if (Reset==0)

            Count_Out <= 4'b000;

        else 

        // when load is high durign a clock puilse, load the value (and don't count)

        if (Load)

        begin

            Count_Out<=Load_Val;       

        end

        // count in the right direction

        // and check for possible (and allowed) rollover

        else if (Up_Down)

            if (Roll_Enable || Count_Out!=15)

                Count_Out <= Count_Out+1;

            else

            begin

            end

        else

            if (Roll_Enable || Count_Out!=0)

                Count_Out <= Count_Out-1;

            else

            begin

            end

    end

    

endmodule

 

//`#end` -- edit above this line, do not edit this line

 

//`#start footer` -- edit after this line, do not edit this line

`endif

//`#end` -- edit above this line, do not edit this line

 

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