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Design 3 Code | Cypress Semiconductor

Design 3 Code

Summary: 0 Replies, Latest post by rahulram on 23 Dec 2012 09:51 AM PST
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rahulram's picture
Cypress Employee
115 posts

 `include "cypress.v"

//`#end` -- edit above this line, do not edit this line

// Generated on 12/17/2012 at 13:40

// Component: FourBitCounter

module FourBitCounter (

output [3:0] Count_out,

output  Max,

output  Min,

input   Clock,

input   Load,

input  [3:0] Load_val,

input   Reset,

input   Roll_enable

);

parameter Max_Count = 0;

parameter Min_Count = 0;

parameter UPdown = 0;

 

//`#start body` -- edit after this line, do not edit this line

 

reg[3:0] count;

assign count = Count_out;

 

always@(negedge Reset) //asynch reset

begin

count=0;

end

 

always @(posedge Clock)

begin

if (Load == 1) begin //Check for load condition

count = Load_Val;

end

 

if  (UPdown==0) begin //check if counting down

if (Roll_enable == 1) begin //check if roll and count regardless

count = count - 1;

end

else begin

if (count > Min_Count)  begin

count = count - 1; //if greater than Min, count 

end

end

end

else begin //counting up is the other option

if (Roll_enable == 1) begin //check if roll and count regardless

count = count + 1;

end

else begin

if (count < Man_Count)  begin

count = count + 1; //if less than Man, count 

end

end

end

end

 

 

always @(posedge Clock) begin //Check for Max condition

if (count >= Max_Count) begin

Max = 1;

end

else begin 

Max = 0;

end

end

 

always @(posedge Clock) begin //Check for Min condition

if (count =< Min_Count) begin

Min = 1;

end

else begin 

Min = 0;

end

end

//        Your code goes here

 

//`#end` -- edit above this line, do not edit this line

endmodule

//`#start footer` -- edit after this line, do not edit this line

//`#end` -- edit above this line, do not edit this line

 
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