You are here

Design 2 Code | Cypress Semiconductor

Design 2 Code

Summary: 0 Replies, Latest post by rahulram on 23 Dec 2012 09:49 AM PST
Verified Answers: 0
Log in to post new comments.
rahulram's picture
Cypress Employee
115 posts

 `include "cypress.v"

 

module Count4Bit_v1_0(

Clock,

Load,

Roll_enable,

Load_val,

Reset,

Count_out,

Min,

Max

);

 

parameter CountUp = 1;

 

input Clock;

input Load;

// input Up_down;

input Roll_enable;

input Load_val;

input Reset;

output Count_out;

output Min;

output Max;

// reg [3:0]Load_Reg;

reg [3:0]Count_out;

reg Load_Flag;

wire [3:0]Load_val;

//`#start body` -- edit after this line, do not edit this line

 

assign Min = (Count_out == 4'h0);

assign Max = (Count_out == 4'hf);

/* */

always @(posedge Clock or posedge Load)

if(Load)

begin

Load_Flag <= 1'b1;

end

else begin

Load_Flag <= 1'b0;

end

/* */

always @(posedge Clock or negedge Reset)

if (~Reset)

begin

Count_out <= 0;

end

else begin

if(Load_Flag)

begin

Count_out <= Load_val;

end

else

begin

Count_out <= CountUp?(Count_out[3:0]+{0,0,0,Roll_enable | ~Max}):(Count_out[3:0]-{0,0,0,Roll_enable | ~Min});

end

end

//`#end` -- edit above this line, do not edit this line

endmodule

//`#start footer` -- edit after this line, do not edit this line

//`#end` -- edit above this line, do not edit this line

 
Log in to post new comments.