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Design 1 Code | Cypress Semiconductor

Design 1 Code

Summary: 0 Replies, Latest post by rahulram on 23 Dec 2012 09:46 AM PST
Verified Answers: 0
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rahulram's picture
Cypress Employee
115 posts

 `define UP 0

`define DOWN 0

 

module up_down_counter(

input clock,

input reset,

input load,

input roll_enable,

input[3:0] load_val,

output reg[3:0] count_out,

output max,

output min

);

parameter up_down = 0;

wire halt = (!roll_enable) & (((count_out == 4'h0) & up_down) | ((count_out == 4'hF) & !up_down));

 

assign max = (count_out == 4'hF);

assign min = (count_out == 4'h0); 

always@(posedge clock or negedge reset) begin

if(!reset)

count_out <= 4'b0;

else if(load)

count_out <= load_val;

else if(~halt)

if(up_down == `UP)

count_out <= count_out + 1'b1;

else

count_out <= count_out - 1'b1;

end

 

endmodule

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