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Checking the source of reset in PSoC3/PSoC5 | Cypress Semiconductor

Checking the source of reset in PSoC3/PSoC5

Summary: 10 Replies, Latest post by SequoiaCPE on 26 Nov 2014 08:58 AM PST
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U2
uday's picture
Cypress Employee
569 posts

 PSoC3/PSoC5 device has  multiple sources which can reset the device.

  • WatchDog
  • Low Voltage Detect Analog, LVI-A
  • Low Voltage Detect Digital, LVI-D
  • Software Reset and so on

Once the device is reset it is possible to identify the source of reset by reading the value of the register, RESET_SR0. However this register is read on clear. When the reset is triggered and the device boots, the device by default waits for bootloader and in the bootloader code this register is read and the status is cleared. However before reading this register the code preserves this register value as a variable, uint8 CyResetStatus.

U2
uday's picture
Cypress Employee
569 posts

Immediatlet after Reset(due tp watchdog timer or software reset) you might read the RESET_SR0 and find that it is zero. By reading the variable CyResetStatus you will be able to identify the source of reset. You can find more about this in the system reference guide(Preservation of Reset Status (PSoC 3 and PSoC 5)).

BMAH's picture
Cypress Employee
224 posts

 Adding one more point to this:

When any LVI reset occurs, the RESET_SR0 and RESET_SR2 status registers are cleared. This means that the Analog LVI, Digital LVI, and Analog HVI status bits are not persistent across any LVI reset. This has been mentioned in the System Reference Guide. Please check the PSoC 3/PSoC 5LP Voltage Detect APIs Section under 'System Functions' of the System Reference Guide (Please check the definition of the API CyVdLvDigitEnable()). 

 However, it is possible to generate an interrupt during LVI/HVI event using the GlobalSignalRef component. You can also set the thresholds by writing suitable values to the CYDEV_RESET_CR0 reg.

It is also possible to reset the device using the LVI/HVI conditions using the APIs provided under 'System Functions' of the System Reference Guide. Please check this for more details.

Regards

PSoC Wonders

user_51922177's picture
User
109 posts

 Can the GlobalSignal component output as an LVI event be routed to a digital output pin for use as a DSO trigger for diagnosing power glitches?

The question arises from using the isr to set an output pin adds a delay that may exceed to time that the DSO is able to display from its memory.

Thanks,

Bruce

user_1377889's picture
User
10803 posts

I do not see anything hindering from routing the LVI signal to a pin.

 

Bob

user_51922177's picture
User
109 posts

 Bob,

A follow-up.

Is the Global signal, as an LVI variety, dependent on the register setting for an LVI causing an interrupt?

Thanks,

Bruce

user_51922177's picture
User
109 posts

 Bob,

I am set up as follows:

Digital output pin driven via a GlobalSignal through a Not component with a resistive pullup on the pin.

If a VDDD drop, the resistive pullup should reflect the VDDD drop event regardless of the GlobalSignal. Trigger may be less than a complete drop. (Without the LVI activated, the Resets I am chasing were most likely PRESx with a ~1.6v default setting, large enough to trigger the DSO.)

If a VDDA signal, the VDDD presence and the GlobalSgnal is still capable of driving the Not component and reflect the VDDA drop event.

Can't wait to get my DSO.

Bruce

user_1377889's picture
User
10803 posts

There are plenty of APIs concerning the LVI. Have a look into the System Reference Guide (to be found in Creator under "Help"

 

Bob

user_51922177's picture
User
109 posts

 Bob,

Again thanks.

The System Reference Guide does answer the GlobalSignal question I posed. It does not introduce the Interrupt/Reset condition and as a result it is unambigous. "If “Low/High Voltage Detect (LVI/HVI)” is selected in the component, the output of GlobalSignalRef is set to 1 whenever any of the enabled LVI or HVI circuits detect an event.". This clearly states the GlobalSignalRef action. I should not need to do anything except to activate the LVI's to be able to use this as a DSO trigger.

 

When I read further down in the SRG under CyVdLvDigitEnable(...), and others, the following statement regarding Resets reads: "When any LVI reset occurs, the RESET_SR0 and RESET_SR2 status registers are cleared. This means that the Analog LVI, Digital LVI, and Analog HVI status bits are not persistent across any LVI reset." This statement does not seem to be in agreement with the section "Preservation of Reset Status" in the same SRG. It references a Global SRAM variable (I assume CyResetStatus).

And even  "Preservation of Reset Status" says that the XRES is implicitly a Software Reset, which I believe to be an error (pressing the CY8CKIT-030 Reset buton causes an SRAM clear which is a hallmark of a Hardware Reset).

 

When my project experiences unexplained Resets intermittantly, and after a close inspection of my code without success, I try to rely on the documentation and Generated Code to help me understand PSoC. I start with the assumption that I have coded some PSoC API or Register setting in error. I have tended to ask for clarification whenever I find ambiguity in the documentation and am unable to shoot the bug. You and others on the Developer Forum have been very patient with me and I fully appreciate that assistance. My experience with other vendors is probably the major reason I switched my project to Cypress PSoC.

 

I am hoping that the soon to arrive DSO is the Light at the End of the Tunnel!

Bruce

 

 

 

 

 

user_1377889's picture
User
10803 posts

Thank you for the flowers! ;-)

 

Keep in mind that you may set the LVI to NOT reset the CPU but to generate a signal or interrupt.

 

Bob

user_51922177's picture
User
109 posts

 Bob,

Testing HVI/LVIA/LVID via GlobalSignalRef shows the signal to be negative logic; the signal is at VDDD when not in a reset and VSSD when a reset. The signal lasts from the start of the reset until main() is executed (Based on visual observation where I use the LED's to indicate startup).

I have removed the Not component since I want a falling edge.

Bruce

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