Voltage Dependence of PSOC3 sleep | Cypress Semiconductor
Voltage Dependence of PSOC3 sleep
I have a simple but very low power application running on a PSOC3. When the device goes into sleep mode it essentially disables everything and sleeps for 1000ms (CyPmSleep(PM_SLEEP_TIME_CTW_1024MS, PM_SLEEP_SRC_NONE);)
and then briefly checks a capsense pin before sleeping again. this has been working fantastically up until now. I recently updated my rev1 board to remove a few things and move 2 or 3 pins around. I have also changed the firmware somewhat, but only functional code, nothing relating to the sleep cycle or hardware at all. Before releasing the product to the customer I thought I should quickly verify that the current draw is in fact as low as it had been.
It's not. Whereas it was previously drawing about 10uA in sleep, its now drawing about 250uA. I quickly changed a few things to see if its something stupid I had done; like leave the debug interface on, wrong clocks or something, i even replaced the PSOC incase it had been an old chip which might have been slightly damaged, but no. I changed the 'SleepTimer_interrupt' example project to my board (simply connect the LED in the example to my LED) and ran it and got the same results -> 250uA. This was with a rather full battery (about 3.5V from a 3.6V lithium cell), so I thought to try other voltages. with my power supply if I give it 3.6V I get the same result, but when I crank it down to 3V the sleep current drops to 20uA??? I saw this response in both the example code and my own. Curiously this is still higher than I remember it being, so I'll do a bit of digging to find my old board and just verify my results.
Could it be that to truly get low power you need to provide an external 1.8V for the VCC lines? this is the only thing I can think of as the internal regulator is clearly still on during sleep.
Has anyone else experienced this?