Using Open Drain, Drives low drive mode as a Digital Input | Cypress Semiconductor
Using Open Drain, Drives low drive mode as a Digital Input
I'm using a CY8C3446AXI-098 PSoC 3, which according to the datasheet has two USBIOs on pins P15 and P15 which can be used to either provide connection for a USB data bus or be used as general DIO pins. However, what the datasheet didn't specify, and what I didn't find out until trying to build my design, is that the DIO pins can only be configured to one of two drive modes, Strong Drive, and Open Drain Drives low.
I was hoping to use these pins as general purpose digital input pins. It seems logical enough to think that the pins could be configured in Open Drain, Drives low drive mode, and simply held in the high-Z state to be capable of sensing any input voltage on the pin. However, if this is the case I would expect to be able to configure the pins as a high impedance digital input drive mode so there would be no confusion. Must the software ensure that the pin is always held in high-Z state when configured as an input, or is this done automatically by PSoC creator?
I just want to verify that a pin configured as Open Drain, Drives low can be used as a digital input equivalent to a high impedance digital input pin with no extra external circuitry or software so that I don't end up building the board and realize these two DIO pins don't act as I'd expect.