Using Input signals in UDB Datapath configuration | Cypress Semiconductor
Using Input signals in UDB Datapath configuration
I am trying to design a simple UDB component which takes two signals (both are 0 or 1) as input and does some logical operations on them. After writing the code in Verilog, when I try to configure the datapath, I need to use the input signals which are defined as 'wires' in verilog. How to load the input signals in the two accumulators so that I can do comparisions on them?
I looked at all the relevent documents and the only hardware input option I can find is through 'Carry In - Route' option. Can anybody suggest something?
Thanks and Regards