Timed SPI Communication for Controlling Remote ADC Sampling Rate | Cypress Semiconductor
Timed SPI Communication for Controlling Remote ADC Sampling Rate
What is the best way to allow the PSoC to control the ADC sampling timing via the SPI interface? Should I setup a timer to execute an ISR to request data, wait for the data, then send data to buffer? I will need the ADC to take 3000 samples at a rate between 40-60 ksps total. Thus at 60 ksps I would need to send "convert" commands every 1/60ksps = 16.6us. Will there be enough time to send the request, wait for the data, and then DMA it to a buffer?
Below is a sample of info from the datasheet. I’ve also attached part of the datasheet.
The RHD2000 ADC samples the selected analog signal on the falling edge of CS. The CS line must be pulsed high between every 16-bit data transfer, even when the command word does not request an analog-to-digital conversion. The RHD2000 samples MOSI on the rising edge of SCLK. The master should sample MISO on the rising edge of SCLK. (The master device SPI interface should be configured with SPI options CPOL=0 and CPHA=0.)
After receiving a CONVERT(C) command from the master, the on-chip ADC samples channel “C” on the falling edge of the next CS pulse. The analog-to-digital conversion is performed during the next 16 SCLK cycles, and the result is relayed to the master over the MISO line during the following 16 SCLK cycles (two total commands later).
The RHD2000 uses a pipelined communication protocol; each command sent over the MOSI line generates a 16-bit result that is transmitted over the MISO line two commands later. Communication with the chip is illustrated in the following example diagram: