Ignoring the first 3 SPI clocks | Cypress Semiconductor
Ignoring the first 3 SPI clocks
I have a design with a SPI Slave, where I don't have the slave select connected.
I've noticed that the master sends three spi clocks before the data I'm expecting on the mosi line, so I clock and extra three bits of garbage.
What's the best way to ignore the first three clocks? I was thinking I could get a ShiftReg of 3 bits to drive the SS on the SPI Slave, but haven't managed to get that working yet.
thanks for any ideas,