DMA split data to seweral destenation adresses. | Cypress Semiconductor
DMA split data to seweral destenation adresses.
I have faced with preaty strange fact.
I'm try`ing to create 10-chanel logic generator, based on counters whith two DMA chanels per each chanell.
first DMA refreshes Counter period (regulates perion lenght), second updates logic level (0/1).
the problem is :
some channels are reflected, some times are reflected and mirrored on another line.
(see pics below)
each pic made with only one active Counter.
Can you tell me where am i wrong, or how to fix this problem?
I'm using CY8C3446AXI-099.
Design is attached.