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DMA maximum frequency supported | Cypress Semiconductor

DMA maximum frequency supported

Summary: 3 Replies, Latest post by PSoC Rocks on 13 Oct 2012 06:19 AM PDT
Verified Answers: 0
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Stillen's picture
1 post


Hi guys, I'd like to ask you a question about the use of the DMA....

For some reasons I need to transfer some data from a status register to the internal memory....the status register value is changed at a frequency of 33MHz (8 digital input pins are linked to the status register).

The problem is that apparently the transfer operation performed by the DMA doesn't fit this high speed since I get less sample than expected (it should fit something like 6 or 7 MHz) my question would be:

is there a maximum clock frequency supported by the DMA (by the drq input)? 

Thank you very much in advance!! ;)


user_1377889's picture
9284 posts

I suppose that might depend on the bus-clock you have configured.

How is you your drq-signal generated and what does your DMA-setup look like?


Best can be if you upload your project here, so we all can have a look at it.

To do so: in Creator 2.1 Build -> Clean Project

File -> Create Workspace Bundle (minimal)

and finally upload the resulting Zip-archieve here (takes some time after pressing the "post" button)




user_14586677's picture
7646 posts

If you look in the Architecture TRM there is an example of computing the number

of buss cycles to do a burst, inclduing its overhead. Bus clock is the prime limiting

factor during the burst. Search in index for PHUB and DMAC.


Regards, Dana.

PSoC Rocks's picture
141 posts

 N+6 for interspoke DMA transfers

2N+5 for intraspoke DMA transfersN -> Burst counts

When there are more than 1 channel requesting a free DMA Controller, the arbitration phase would take more cycles and it uses Grant allocation Fairness Algorithm for allocation of channels.




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