DFF issue with SPI | Cypress Semiconductor
DFF issue with SPI
I made a simple circuit with a SPI master followed by a D-flip-flop. Please see attached image.
When I press a button the SPI will transmit the byte: 0xAA
I noticed that the DFF seems to latch the D input on the falling edge of the clock, which was not what I expected.
I've used DFF's often in PSoC design and they normally latch on the rising edge.
Please note I'm running at only 5 Hz SPI clock to be able watch the LEDs on the dev kit.
What's wrong here?