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BaseCounter Component? | Cypress Semiconductor

BaseCounter Component?

Summary: 3 Replies, Latest post by McBadger on 21 Oct 2014 02:04 PM PDT
Verified Answers: 0
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user_377526869's picture
13 posts

I'm working on a project where I'd like to have a counter increment with a base other than 1, i.e.:

 A = A+Base

So far I've used a PulseConverter and TFF to convert the single pulse to Base pulses into a Counter UDB component, which sort of works, but of course takes Base clock cycles to increment.

Any better solutions?

I'm currently looking at the UDB Editor to see if I can make one there directly.





user_14586677's picture
7646 posts

Consider the DFB Assembler, that allows you to control

a single cycle MAC and would be a natural for your re-



Note any recomendation is highly dependent on some other

questions, like what is the speed you need for the counter ?


Regards, Dana.

user_1377889's picture
9281 posts

You can do that in VeriLog, but that is a bit challenging for a beginner. There is a "Component Author Guide" referring to verilog and a verilog guide already installed in your Cypress folder. Additionally some videos will guide you, look



user_377526869's picture
13 posts

 Thanks for the quick replies.

I'm trying to run at BUS_CLK (32MHz), as the counter En is driven from a TERMOUT signal, and the COUNTER value gets read by a different DMA (64-2080 cycles later).

I've started playing with the UDB Editor and have a small component that I'm trying to test.

Did also create one Verilog component as an example.

Just wanted to check I wasn't looking over a more obvious solution.





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