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Addition Overflow Detect | Cypress Semiconductor

Addition Overflow Detect

Summary: 3 Replies, Latest post by ObsoleteMindTech on 23 Dec 2010 01:12 PM PST
Verified Answers: 0
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ObsoleteMindTech's picture
3 posts

I'm new to the PSoC system, and to programming for the 8051 core in general. However, I've been working on 8-bit MCUs for a while now. Mostly in ASM, so I'm used to having a lot of access to the MCUs flags and such.

What I want to do is add a small error correction value inside and ISR and have another value adjust when the 8bit error counter overflows.

uint8 ErrAdjust = 8; // Pre-calculated error adjust (changed by software)

    static uint8 errValue = 0;
    errValue += ErrAdjust;

    if (__carry_bit__)
        // Adjust another value

How should I go about this. Keep in mind that I'd like it to be as efficient as possible.

kiku's picture
Cypress Employee
64 posts



Please go thorough the Application Note on Interrupts handling in PSoC3 over <a href = "">here</a>.


You need to add your custom code in the specified section (Between Start and Stop).




user_93359284's picture
25 posts

 It looks and sounds like you are trying to apply asembly programming constructs to the C language.

If you state what it is you are trying to achieve (not just how you are trying to achieve it) then it will help.

In C there is no concept of a carry flag, but there are various ways to detect if an 8bit add has overflowed. However, it's unusual to do that in C, which makes me think there would be a better way to approach whatever it is you are trying to do.

However, to detect if an unsigned 8 bit add has overflowed, you could check to see if the result was smaller than you started with - that would indicate an overflow. Or you could use a signed 8 bit value, and check the sign after the add. But like I said, it's pretty unusual.

Best wishes,


ObsoleteMindTech's picture
3 posts

My reason for doing something like this is to adjust timing accuracy for a slower frequency output.

I am generating a sinewave output at between 0.1 and 50.1 Hz, with 0.1Hz accuracy. To update the sinewave sample I am using a 16-bit counter, running at about 75kHz. The counter's period is filled with a value calculated to give 180 samples per wave. So a 10Hz wave would have a count of 41.667. Using a count of 42 produces a sine wave at 9.9Hz. That error is unacceptable.

So to solve it I have 2 values: a count of 41 and an 8-bit error correction value. In assembler (which is what I'm more familiar with) what I would do is recalculate that error of .667 into 171 by multiplying by 256 (all of these values are precalculated anyway). Then every sample I add the error value to a rolling 8-bit counter. When the counter rolls over the counter period is updated for a period of step+1. The samples have a small amount of jitter (+/-13us) but the overall waveform has a very accurate frequency.

I know that this can be done by using a 16-bit rolling counter, checking for values above 255 and then subtracting 256, but that adds extra overhead I don't want.

static uint16 errTotal = 0;

errTotal += errValue;
if (errTotal >= 256)
    // Not Efficient Rollover     errTotal -= 256;

I know with some other 8-bit processors (such as Freescale) their compiler has built-in macros that allow for quick checks of some of the accumulator status bits. Specifically the carry bit. I've written my previous example code in C for the freescale micro almost exactly as above. What I want to know is if I can do something similar for the PSoC, or if I have to use the less efficient workaround.

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