Verilog in PSoC3 - Sharing Variables | Cypress
Verilog in PSoC3 - Sharing Variables
Summary: 3 Replies, Latest post by abnoname on 12 Jan 2012 01:10 AM PST
Verified Answers: 1
11 Jan 2012 07:29 AM PST#1
So I'm trying to have code set some variables(an array,to be specific) in a verilog file,and the verilog code will then process that data,and clock out that processed data.How do I go about doing so?