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Verilog in PSoC3 - Sharing Variables | Cypress

Verilog in PSoC3 - Sharing Variables

Summary: 3 Replies, Latest post by abnoname on 12 Jan 2012 01:10 AM PST
Verified Answers: 1
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user_66945721's picture
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256 posts

Hey,

So I'm trying to have code set some variables(an array,to be specific) in a verilog file,and the verilog code will then process that data,and clock out that processed data.How do I go about doing so?

user_66945721's picture
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256 posts

I only have a few hours of Verilog experience,so I'll ask a few stupid questions on your replies.Just saying. :-P

user_66945721's picture
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256 posts

by code setting variables I mean C code setting variables in some way which the verilog file can use them.

abnoname's picture
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46 posts

 CPU (software) and hardware interaction (this is what you want) will work through status and control registers. For example you can instance a control register which will provide an api for cpu access and a digital out bus on the hardware side.

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