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Use of P1 for both debugging/programming and GPIO | Cypress Semiconductor

Use of P1 for both debugging/programming and GPIO

Summary: 3 Replies, Latest post by H L on 16 Jun 2013 06:10 AM PDT
Verified Answers: 0
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ado's picture
23 posts

In our current research project I need to use the debug pins on P1 temporarily for another purpose under

program control.


So I want to be able to disconnect the pins from the JTAG/SWD and connect them to some other circuitry under software control.

However, PSoC creator does not let me do it unless I have switched to "GPIO" in the debug section (Programming\Debugging->Debug Select)  in the system tab.

I have searched through the TRM and only found the hint in Section 39.5 of the PSoC 3 TRM:

"Two NV latch bits determine the state of the JTAG/SWD interface pins at reset" 

But it does not say whether this can be changed later.

I want the pins active as debug on startup, but I want to wire them to internal circuitry.

Since the acquisition of the test controller is such a protected activity I am sure that my external circuits will not

interfere with the debugging function until my application software runs and can control the enable/disable of the debugging functionality.


I am not sure whether this is problem of PSoC Creator or the architecture that's why I ask here.





PSoC Rocks's picture
141 posts

Refer to NVL section of the datasheet (Page No - 23 001-11729 Rev. *W) to find out the location of the register which is used for Debugging port selection (5-wire JTAG, 4-wire JTAG, SWD or GPIO).

NVL has very low endurance of about 1K cycles when programmed at 25deg C. So it is not recommended to keep changing the NVL bits of the device.

user_460349's picture
1362 posts

 I would try not to use NML to often, as that only has a very small number of changes is allowed. I tmay cause you chip power up in a unwant state if over used.

user_14586677's picture
7646 posts

This might be of assistance -


Regards, Dana.

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