Timing constraints for digital routing | Cypress Semiconductor
Timing constraints for digital routing
we have a timing sensitive design (part of it), that is hand optimized for max performance (highest possible clock) to meet the setup and hold timings. Most other parts do have much lower requirements. It seems that cydsfit will optimize all parts with the same rules.
Is there a way to define a timing constraint for some signals or clock domains, that will become a much higher priority while routing over others?
We also designed the project with Creator 3.0. After updating to 3.3 the timing results a much lower. Therefore we had to switch back, because the design is tested and in production.