THA: variable offset- causes and solution | Cypress Semiconductor
THA: variable offset- causes and solution
In THA, I see a variable offset in the output. The offset is: +10mV at 0V input and -30mV at VDD input. what is the reason for this behaviour? How to avoid it?
When a Track and Hold Amplifier changes from track mode to hold mode, the channel charge present in the switch (when it was ON) will be dumped into the Hold capacitor.
This causes a finite offset in the voltage across the hold capacitor. To minimize this offset, the hold capacitor will usually be chosen larger. This offset is signal-independent in most cases.
To eliminate this offset at the output of the ADC, we can use Correlated Double Sampling (CDS). It is a kind of high-pass filtering that removes DC offset and minimizes 1/f noise.
First, measure the input signal using ADC after sampling and let it be Vsig.
Then, measure the ADC output by giving a known reference(Vref). Here,
Vref is usually at ground potential.
Please do this calibration in firmware to remove the THA offset.
The -ve offset at Vdd input is due to the voltage swing limitation at the opamp's output. To eliminate this offset, we need to insure that the input voltage doesn't exceed the limit which makes the output voltage go above max. output voltage(specified in the datasheet) of opamp.