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Re-Sync SPI bus | Cypress Semiconductor

Re-Sync SPI bus

Summary: 1 Reply, Latest post by kiku on 28 Dec 2010 09:36 PM PST
Verified Answers: 0
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Rog61's picture
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I'm using a PSoC3 dev kit as a SPI master talking to my project board.  To get the SPI bus synced between them I hold the reset on the dev board then reset my project board then release reset on the dev board and they are in sync.  In the future the dev board will be a main controller board and this will need to work on power up.

I would like my project board to sync with the dev board automatically when it's reset and possibly in between packets at runtime to correct bit errors.  My question is does the SS re-sync the slave SPI?  Doesn't seem to.  Can the SS be connected to the Slave Reset signal to reset/resync it between packets?  If not is there another way to do thi?.  I also tried resetting the slave using a timer tc that would expire if the SPI master CLK was inactive (during reset). 

Another thing, if the reset signal is used on the Slave SPI component does the Start(); function need to be called after every reset?

kiku's picture
Cypress Employee
64 posts



Use one control register and connect its output to reset pins of SPI master and slave. Keep the initial value in the control register as 1. So after starting all the modules, you can write 0 into this control register. which will start both the modules at the same time and you won't face the Synchronization issues.




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