qestion on I2C register | Cypress Semiconductor
qestion on I2C register
As my experiment on EZI2C.
1) PSoC3 I2C_CSR.bit3 (address) (0x49d7) was descripted in TRM as be cleared by firmware writing '0'.
But in EZI2C_INT.c generated by creator, ISR function never write this bit '0' to clear it. Is this bit will be cleared by any accessing instead of writing '0' ?
2) The I2C interrupt mask never be mentioned in TRM, it seems built in UDB, is it? If any MASK register exist, what's the initial/reset value, since I have not found any configuration in EZI2C_Start().