Pulse SPI SS line using hardware | Cypress Semiconductor
Pulse SPI SS line using hardware
I'm sending 16bit data using SPI without any delay between data. Thus, the SS line never switches high/low to denote the start and stop of data. This is causing errors on my slave device because it is expecting the SS line to pulse high between data.
I tried software solutions but the timing isn't accurate enough. Because my data is sent without delay the SS line pulse must fall between the falling edge of the 16th clock and the rising edge of the next clock cycle.
I'm looking for suggested solutions and for comments on my next attempted solution below.
I plan to to test a counter with the SPIM clock as input. The counter will count 16 clock cycles. Output of the counter will go into a rising edge detector. Both the counter and edge detector will use much faster clock than the SPIM. Output of the edge detector will be used for SS line. Seems like it may work from the datasheets. I'll post back with results.