# Cypress Developer CommunityTM

## PSoC3/5 VDACs, a bit more flexible than you think

Summary: 9 Replies, Latest post by Archimedes on 28 Nov 2011 08:21 AM PST
Cypress Employee
730 posts

Hi All,

I just read this blog post by Mark H and thought that it's a great idea to share it with everyone.

Remember way back when you were learning about voltage and current sources, you were told it was bad to put voltages sources in parallel and current sources in series.  These are good rules, but often a voltage source is not exactly and “ideal” voltage source.  Take the PSoC 3/5 VDACs.  At first glance they seem like a typical voltage source and you would never think about putting them in parallel.  If you look under the hood, you will find that this voltage source is really a current source with a resistor.  When the VDAC range is selected to be 1 volt, it is equivalent to an IDAC in the 256uA range with a 4K resistor connected between the output and Vss.

So you might say “so what?”  This means we can actually put two VDACs in parallel and not violate the law of parallel voltage sources.  In the diagram below you can see that two parallel VDACs in parallel really look like a single IDAC with double the current output with a 2K load to Vss.  The 2K resistor is the result of two 4K resistors in parallel.

If each of the VDACs (VDAC8_1 and VDAC8_2) generate a separate waveform and the VDAC outputs are connected, we simply get the average of those two signals.  Take a look at the scope image below where the two upper traces are the two individual VDAC output. The third signal on the bottom is the output of these two signals when the DACs are connected in parallel.

Just to have a bit more fun, do you remember when you learned about Fourier series?  I remember how cool I thought it was the first time we looked at the FFT of a square wave and learned the relationship of the harmonics to input square wave.  Looking at just the first four harmonics we get the equation below.

We then had to write a program to prove this and display it graphically.  With PSoC you can prove it just by connecting four VDAC8s in parallel.  As you can see in the image below, the upper four sine waves are averaged together to create the pseudo square at the bottom.  Wish I had a PSoC back in school about 30 years ago.

This is just a handy trick when you need to average two or more individual signals in hardware and don’t want to use any external components.

Note:

VDACs can be used to generate periodic waveforms by making use of RAM/ROM lookup tables that are transferred to the VDAC either with the CPU or with DMA.

User
48 posts

Does this mean that we could get a higher resolution VDAC in this method? For example, if we fed a high impedance input, could we use two parallel 1V range VDACs to do a similar function as the parallel IDAC mentioned in one of the application notes?

Thanks

User
2551 posts

Yes, this should work (and I think that this was stated in the original post as well, but I'm not 100% sure).

Cypress Employee
730 posts

Hi Diode Dan,

Ideally, it is possible to obtain a higher resolution current output DAC by summing the outputs of two 8-bit current DACs, each having a different segment of input bus for input. The range of the two DACs partially overlap.

Consider the following situation where a 12-bit DAC is implemented using two 8-bit DACs.

Here, one DAC is scaled to the range of 0-2.048mA and the second one to the range of 0-32uA

The middle 4 bits of the lower range DAC are used as inputs to the lower 4 bits.

Cypress Employee
730 posts

This architecture may have problems of mismatch in the two DACs and hence may require adjustment and scaling.

The last two bits of the LSB DAC are used for minor calibration adjustments.

User
23 posts

Since the individual DACs would have been trimmed for thier own linearity there might be case of non monotonocity while this architecture is used. A solution could be to use the onboard ADC in the device to one time calibrate out such DNL points.

In fact there are the unused bits in the second DAC that can provide some calibration room.

Cypress Employee
53 posts

If you are interested in easy waveform generation, you should take a look at application note AN69133.   It includes the WaveDAC8 component that will generate a continuous waveform with just one line of code and no CPU overhead.  It takes care of the lookup table and the DMA so you don't have to.  Also it has a nice GUI to make configuration easy.  It also supports both current and voltage modes of the DAC with a single component.  Download the application note and example projects and take it for a spin.

If you need a bit more resolution, there is another application note that covers that, AN64275.  This application note shows you a couple different methods to increase resultion and provides a component for three of these methods.

Mark

User
48 posts

Hello Everyone,

Thanks for your replies. I think people have misunderstood the point of my post. I have read the application note detailing how to get more resolution from a DAC and the blog post explaining the VDAC architecture. The parallel IDAC method is a good method, but requires an external resistor.

What I was thinking was to change the range of the IDAC sourcing the internal resistor for the VDAC. Lets say we have two VDAC components. I should be able to modify them such that they both use the 1K resistance and one uses the 255uA range while the other uses the ~32uA range. These overlapping current ranges would create the higher resolution, and the parallel resistances would simply divide by 2.

This would have the benifit of providing the extra resolution from the IDAC, while at the same time preventing us from having to use external resistors and route off the chip.

I hope this helps explain what I want to do in more detail. Here, I don't update any faster that 1kHz, so speed is not the most pressing issue (I hope).

Thanks

Cypress Employee
730 posts

Hi Diode Dan,

Theoritically, the resolution can be increased by the technique you have stated.

Say, the two internal resistors of 4K are used, then a parallel combination will yield a 2K ohm resistor.

As you have mentioned, if we assume that one current source is sourcing in 255uA range and the other in 32uA range, then the last 3 bits of the 32uA range source will add extra 3-bit resolution.

However, this technique has a disadvantage. Non gain mismatch in the two DACs will result in non-linearity and unequal step size. To compensate for this, trimming registers DACx_TR should be used for calibration.

User
23 posts

When you use a VDAC mode on the DACs you are stuck at having a resistor of 4k or 16k based on range and the current is always a 256uA setting. It would have been great if there was control over the current ranges when using the VDAC mode.