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PSOC3 counter difficulty | Cypress Semiconductor

PSOC3 counter difficulty

Summary: 3 Replies, Latest post by Gautam Das on 27 Jan 2011 06:19 AM PST
Verified Answers: 0
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CHRISTOPHE's picture
2 posts


I use a "Up and Down" counter ( 32 bits ) configured as follows :

-period : 4294967295 (2^32  - 1)

-clock mode : count input and direction

-run mode : continuous

-reload counter on "reset" and on "tc"

Besides my input pin is configured in "resistive pull down" as drive mode, my goal is to count rising edge of a rotary encoder (in order to know the position of a robot), however my problem is when I turn my encoder the counter increment too fast whereas I turn a little bit the encoder. What's the problem ?


PS : I'm French what explain the quality of my English, I joined the project with the post, the name of the counter is "Counter_debug" in the PSOC Creator project!

StefanL's picture
6 posts

A rotary encoder will likely have glitches on the output as it is being turned which could be seen as a rising edge. Are you doing glitch detection / filtering?



CHRISTOPHE's picture
2 posts

No, I didn't. But I generated a PWM signal with a period of 1 second (with the PSOC itself) and I connected this signal at the input of the counter.And it increment too fast in this case too ( about 1 000 000 steps on a rising edge of the signal).

dasg's picture
Cypress Employee
730 posts



Which version of the Counter component are you using?

Is it version 1.2 or version 1.5?




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