PSoC 3 Pending Interrupt | Cypress Semiconductor
PSoC 3 Pending Interrupt
I have noticed the following interrupt behavior on my PSoC 3 ES3 and am trying to understand it.
I have an edge triggered ISR component connected to a digital line (I'll call it ISR1).
Given the following sequence:
- Starting at power up (interrupt enable bit for ISR1 and global interrupt are not set by default)
- Interrupt source occurs, setting the pending flag for ISR1
- Call ISR1_Start();
- Call ISR1_Stop();
- Call ISR1_ClearPending();
- Call CyGlobalIntEnable
When CyGlobalIntEnable is called, the isr for ISR1 is immediately executed. Checking the INTC_CLR_EN and INTC_CLR_PD registers confirms that ISR1 is neither enabled nor pending when global interrupts are enabled.
I assume the interrupt is pending somewhere in either the interrupt controller or CPU, but I have been reading the TRM and cannot determine where it is pending or how to clear it. Any insight on this is appreciated.
Note: I can 99% solve the problem by moving the ClearPending before the Start, so ISR1 is not enabled and pending at the same time. But this is not really a solution as there is a small chance the interrupt could be triggered during the period between Start and Stop. Plus I would like to understand what is actually happening.