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PSoC 3 D-S ADC Clipping | Cypress Semiconductor

PSoC 3 D-S ADC Clipping

Summary: 1 Reply, Latest post by Stub for 42107979 on 20 Sep 2011 05:23 AM PDT
Verified Answers: 1
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user_150737060's picture
9 posts

Hello all,

I feel like someone has probably asked this question already, but I couldn't find it, so apologies if this is a duplicate.

After reading the datasheet, my understanding is that to avoid the nonlinearities near the rails, the ADC attenuates the input by 10% then applies a gain of 1.11 afterwards. Since you can still drive it to the rails, the output can exceed the specified ADC resolution. This is a problem as I want to sample 16-bit data (which actually returns 17-bits). The datasheet suggests that I read a 32-bit value to account for potential overflow. This is less than ideal, as I am trying to buffer quite a bit of data and can't afford to fill half my memory with zeros. I could also look at each sample as it is collected and apply the clipping in an ISR, but I would very much prefer not to do that and to use DMA instead.

Another option is to collect 15 bits instead, so I know it will safely fit in 16 bits. This presents me with other problems as 15-bit sampling requires a higher sampling rate than 16-bit which doesn't fit within my timing scheme. Plus I'd be wasting a bit that will only be used 0.0001% of the time. Since I'm not interested in measuing values beyond the rails, my preferred solution is to find a way to clip the output so that rather than using 17 bits, the output will saturate at 16 bits.


In short: Is there a way to automatically clip (saturate) the 17-bit output of the 16-bit ADC to guarantee it will fit in 16 bits? If there is no easy way, any suggestions on the best path to the hard way? This chip has an incredible amount of configurabililty that I'm still learning, but it seems like there is probably a solution in the configurable logic.

Thanks for your help,

-- Jonathan

Stub for 42107979's picture
19 posts

 Hi Jonathan,

The 16-bit ADC in +/-1.024V exactly behaves this way:

gives 0x0000 for 0V input, 

0x7FFF for 1.024V input 

and saturates at 0x917D for a 1.136V input.

If you limit your input to < 1.024V, you'll never get output greater than 0X7FFF and a 16-bit variable will just do the job for you. If your input goes higher than 1.024V by any chance, then there is a problem, the ADC outputs a count greater than 0x7FFF and you will interpret it as a negative voltage when actually it was not. 

In single ended mode(0-1.024V) too, we have the same problem. We can trasfer the values  through DMA  into a UDB datapath and perform saturation arithmetic. But, it'll be an advanced concept for you to implement yourself.

I'd suggest you to limit your input or use the 15-bit ADC. Note that the 15-bit ADC can be configured to sample data at rates equal to 16-bit ADC, though the maximum sample rate of 15-bit ADC is higher than 16-bit ADC.

If you prefer using the saturation logic, please file a cypress tech support case. 











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