PSoC 3 D-S ADC Clipping | Cypress Semiconductor
PSoC 3 D-S ADC Clipping
I feel like someone has probably asked this question already, but I couldn't find it, so apologies if this is a duplicate.
After reading the datasheet, my understanding is that to avoid the nonlinearities near the rails, the ADC attenuates the input by 10% then applies a gain of 1.11 afterwards. Since you can still drive it to the rails, the output can exceed the specified ADC resolution. This is a problem as I want to sample 16-bit data (which actually returns 17-bits). The datasheet suggests that I read a 32-bit value to account for potential overflow. This is less than ideal, as I am trying to buffer quite a bit of data and can't afford to fill half my memory with zeros. I could also look at each sample as it is collected and apply the clipping in an ISR, but I would very much prefer not to do that and to use DMA instead.
Another option is to collect 15 bits instead, so I know it will safely fit in 16 bits. This presents me with other problems as 15-bit sampling requires a higher sampling rate than 16-bit which doesn't fit within my timing scheme. Plus I'd be wasting a bit that will only be used 0.0001% of the time. Since I'm not interested in measuing values beyond the rails, my preferred solution is to find a way to clip the output so that rather than using 17 bits, the output will saturate at 16 bits.
In short: Is there a way to automatically clip (saturate) the 17-bit output of the 16-bit ADC to guarantee it will fit in 16 bits? If there is no easy way, any suggestions on the best path to the hard way? This chip has an incredible amount of configurabililty that I'm still learning, but it seems like there is probably a solution in the configurable logic.
Thanks for your help,