Optimizing your C code for PSoC 3's 8051 CPU | Cypress Semiconductor
Optimizing your C code for PSoC 3's 8051 CPU
One of the most frequently encountered probelms while writing a C code for an application is that you may run out of code space, RAM space. PSoC 3 has relatively smaller SRAM (8 KB), Flash (64 KB) compared to PSoC 5 devices. Depending on the application you may typically end up needing to,
1.)Optimize SRAM memory utilization
2.)Optimizing Code space
3.)Reducing Code execution time for a code snippet or an Interrupt routine
The 8051 CPU has some very simple yet powerful features for solving above three scenarios. Refer the application note
<a href="http://www.cypress.com/?rID=40986">AN60630 - Optimizing 8051 Code in PSoC® 3 </a>. It explores the 8051 architecture with regards to above points and also explains how Keil compiler supports these features.
The Keil compiler help manual that comes with Creator is another excellent source of reference.
As an example, 1-bit flag variables that can either be only '1' or '0' can be declared as "sbit" rather than a byte.
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