Limiting intraspoke DMA transfer burst count to <=16 | Cypress Semiconductor
Limiting intraspoke DMA transfer burst count to <=16
Intra-spoke DMA of > 16 bytes requires a ping-ponging of servicing between the source and destination engines within the DMA logic. The reason is there is a 16 byte internal FIFO that fills up by the source engine after which control is switched to the destination engine to empty that out. This is repeated until the burst is satisfied. This ping-ponging has to occur because both engines are operating on the same spoke.
This normally works fine. But, if a previous DMA request is still being serviced by the destination engine and before the request is finished, the source engine for the new request may hit the FIFO limit. At that point since the destination engine is still working on an old DMA context it doesn't yet signal that the new request is an intra-spoke DMA. In the absence of this indication the source engine fails to send a "go" signal to the destination engine to empty out the FIFO for the new intra-spoke DMA request. The destination engine therefore sits idle and this causes the source engine to hang indefinitely since there is no room in the FIFO to do anymore work.
So its always better to have burst count <=16.